Advanced Gate Technologies for Deep-Submicron CMOSFETs

The VLSI layout designing is a highly complex process and hence a layout is often subjected to Layout Verification that includes (a) Design Rule Checking to check if the layout satisfies various design rules and (b) Connectivity Extraction to check if the components of the layout are properly electrically connected. In this work we study two geometric query problems which have applications in t...

This paper describes the restructuring of VLSI education at Royal Institute of Technology (KTH). Changing needs of industry, advances in technology and design methodology has required a significant reorganization of VLSI education with combined emphasis on system issues and associated physical constraints. We present here a course structure which will address in parallel fashion the key design ...