High leakage current in deep sub-micron regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, leakage control and reduction are very important, especially for low power applications. The reduction in leakage current has to be achieved using both process and circuit level techn...

We address disturbs due to gate oxide and junction leakage currents in floating gate nonvolatile memories (NVM). The junction leakage is important, because the gate oxide current is proportional to junction current. We find the low gate leakage current to be caused by field ionization (FI) from traps within the gate oxides. Such low gate leakage currents can lead to sufficient charge accumulati...

The economic and environmental losses due to serious leakage in the urban water supply network have increased the effort to control the water leakage. However, current methods for leakage estimation are inaccurate leading to the development of ineffective leakage controls. Therefore, this study proposes a method based on the blind source separation theory (BSS) to calculate the leakage of water...

Insulation degradation leading to leakage current flow through the high voltage insulator is a major problem faced by various power distribution utilities. The excessive leakage current flow into the wooden supporting structures (wooden cross-arm and pole) leads to pole-top fires and subsequently power cut-off. Most prior researchers focused on flashover phenomena of insulators rather than inve...

Leakage power is the main dominant source of power dissipation for Sub-lOOlJm VLSI circuits. Various techniques were proposed to reduce the leakage power dissipation; one of these techniques is Multi-Threshold voltage. In this paper, the exact and optimal values of Threshold Voltage (Vth) for each transistor of the design are found for any sequential circuit. This is achieved by applying Artifi...

This paper deals with design opportunities of Static Random Access Memory (SRAM) for low power consumption. Initially three major leakage current components are reviewed and then for a 6T SRAM cell, some of the leakage current reduction techniques are discussed. Finally double finger latch is analyzed and compared with single finger latch which shows reduction in sub threshold leakage current.