This paper proposes an algorithm called probabilistic rotation scheduling which takes advantage of loop pipelining to schedule tasks with uncertain times to a parallel processing system. These tasks normally occur when conditional instructions are employed and/or inputs of the tasks influence the computation time. We show that based on our loop scheduling algorithm the length of the resulting s...

In this paper, we present data threaded execution, a new strategy to exploit pipelining and intra-operator parallelism in a shared-everything environment. Data threaded execution is very intuitive, straightforward to realize, and resistant against workload estimation errors and against the dis-cretization error of processor scheduling as it appears in conventional strategies. Furthermore, data ...

In this paper, we consider the problem of scheduling a set of instructions on a single processor with multiple pipelined functional units. In a superscalar processor, the hardware can issue multiple instructions every cycle, providing a fine-grained parallelism for achieving order-ofmagnitude speed-ups. I t is well known that the problem of scheduling a pipelined processor with uniform latencie...

1 Background and Introduction Fine-grain scheduling based on software feedback 3] was introduced in the Synthesis operating system 4, 2] to solve two problems: the dependency between jobs in a pipeline and the low-latency requirements of multimedia type applications. The performance level achieved and the adaptive-ness of applications running on Synthesis demonstrated the success of ne-grain sc...

Multiprocessor system-on-chip (MPSoC) is an attractive solution for increase in complexity and size of embedded applications. MPSoC is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a complex electronic system. While embedded systems become increasingly complex, the increase in memory access speed has failed to ...

The computing-intensive data mining (DM) process calls for the support of a heterogeneous computing system, which consists of multiple computers with different configurations connected by a high-speed large-area network for increased computational power and resources. The DM process can be described as a multi-phase pipeline process, and in each phase there could be many optional methods. This ...

the present sought to draw a comparison between model predictive control performance and two other controllers named simple pi and selective pi in controlling large-scale natural gas transport networks. a nonlinear dynamic model of representative gas pipeline was derived from pipeline governing rules and simulated in simulink® environment of matlab®. control schemes were designed to provide a s...

Out-of-program-order execution has become almost a ubiquitous characteristic of modern processors because of its ability to tolerate variable memory-instruction latency. As designs are becoming increasingly power-conscious, the cost and complexity of the components of out-of-order execution are becoming problematic. Compilers have generally proven adept at planning useful static instruction-lev...

With the rapid development of integrated circuit design technology and the processed tasks and data volumes growing, MPSoC is becoming increasingly popular in a variety of applications. In MPSoC design, parallelism is a very important issue, for example, how to realize task parallelism and data parallelism. Focusing on this issue, this paper analyzes the role of DMA and presents an ILP-Based DM...

Computation intensive DSP applications usually require parallel/pipelined processor in order to achieve specific timing requirements. Data hazards are a major obstacle against the high performance of pipelined systems. This paper presents a novel efficient loop scheduling algorithm that reduces data hazards for those DSP applications. Such an algorithm has been embedded in a tool, called SHARP,...