Pipelines carry different types of petroleum products from production areas to long-distance terminals. This paper introduces a novel Mixed Integer Linear Programming (MILP) based on a continuous time representation for scheduling a multi-product pipeline system connecting a unique refinery to several distribution centers where the mid-terminals are able to both inject product into the pipeline...

Tomasulo’s algorithm creates a dynamic execution order that extracts a high degree of instruction-level parallelism from a sequential program. Modern processors create this schedule early in the pipeline, before operand values have been computed, since present-day cycle-time demands preclude inclusion of a full ALU and bypass network delay in the instruction scheduling loop. Hence, modern sched...

Real-time applications that process streams of data can be modelled by a pipeline of tasks, to be executed on a multi-processor system. The pipeline is periodically activated, and each instance must be completed before an end-to-end deadline. Three important problems must be solved by real-time designers: how to allocate tasks to processors, how to assign scheduling parameters to tasks, and how...

This paper presents a project that provides both, to professors and to students, a tool that is useful for studying, teaching and learning how pipelines work and how they can be scheduled in an easy and widespread way. The project is called PipeSim, and features static and dynamic pipelines with a very attractive, dynamic and intuitive interface. It is well known that pipeline and pipeline-sche...

Reducing the data cache stalls is getting more important as the gap between the CPU speed and the memory speed continues to grow. Many compiler-based techniques including prefetches have been proposed to mitigate the problem for numerical loops, but they are not very applicable to nonnumerical integer loops. One simple idea applicable even to those loops is separating cache-missing loads and th...

Minimizing the response time to asynchronous events in a real-time system is an important factor in increasing the speed of response and an interesting concept in designing equipment fast enough for the most demanding applications. The present article will present the results regarding the validation of the nMPRA (Multi Pipeline Register Architecture) architecture using the FPGA Virtex-7 circui...

Pipelines provide an economic fluid transportation mode for petroleum systems, especially when large amounts of petroleum derivatives have to be pumped for long distances. The system reported in this paper is composed by an oil refinery, one multiproduct pipeline connected to several depots and to the local consumer markets that receive large amounts of oil products. Extensive distances must be...

This paper addresses the problem of developing an optimization structure to aid the operational decision-making in a real-world pipeline scenario. The pipeline connects an inland refinery to a harbor, conveying different types of commodities (gasoline, diesel, kerosene, alcohol, liquefied petroleum gas, etc). The scheduling of activities has to be specified in advance by a specialist, who must ...

A SMT processor can fetch and issue instructions from multiple independent hardware threads at every CPU cycle. Therefore, hardware resources are shared among the concurrently-running threads at a very fine grain level, which can increase the utilization of processor pipeline. However, the concurrently-running threads in a SMT processor may interfere with each other and stall the CPU pipeline. ...

Hiroaki Harai and Masayuki Murata y Communications Research Laboratory, Tokyo, Japan z Osaka University, Osaka, Japan Abstract We investigate the mechanism of high-speed buffer management for output-buffered photonic packet switches. We propose a buffer management mechanism on parallel and pipeline processing architecture consisting of log N pipeline stages, whereN is the number of ports of the...