A recent trend in low power design has been the employment of reduced precision processing methods for decreasing arithmetic activity and average power dissipation. Such designs can trade off power and arithmetic precision as system requirements change. This work explores the potential of Distributed Arithmetic (DA) cornputation structures for low power precisionon-demand computation. We presen...

Due to miniaturization of circuits mobility degradation, velocity saturation and power dissipation issues are critical in the design of VLSI circuits. In this paper various techniques to minimize power dissipation due to glitches are discussed. Total power consumption consists of two major parts like static power consumption and dynamic power consumption. In the total power, the static power is...

Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance ...

Recently, several power estimation techniques have been proposed. Some of them can be used to accurately estimate power dissipation provided that the exact signal probability probability of a signal being logic ONE) and signal activity (probability of signal switching) of primary inputs are known. In general, very accurate specification of primary input signal probability and activity may not b...

This paper describes the system design of a lowpower wireless camera. A system level approach is used to reduce energy dissipation and maximize battery lifetime. System properties such as the network configuration and data statistics are exploited to minimize computational switching. Embedded power supplies systems are also used to minimize energy dissipation under varying temperature, process ...

Introduction: Recently, VCSELs have received considerable interest for short-distance optical interconnects owing to their small footprint, natural occurrence in arrays and, most importantly, cost effectiveness. Two of the main challenges for the devices to be used in board-toboard and chip-to-chip interconnects are speed and power dissipation. For directly modulated lasers, higher speed can be...

A distribution-graph based scheduling algorithm is proposed together with an extended tree growing technique to deal with the problem of unequal-length block-test scheduling under power dissipation constraints. The extended tree growing technique is used in combination with the classical scheduling approach in order to improve the test concurrency having assigned power dissipation limits. Its g...

The demand for powerfiil computational niacliines using scaled technologies has brought power dissipation to the forefront. Hence. there is a need to accurate11 niodel power dissipation in such teclmologies where both capacitive and inductive effects are iniportant. In this paper. we accurately model short-circuit power dissipation of an inverter driving an RLC load. A closed fonii expression i...

The effects of adhesion hysteresis in the dynamic-dissipation curves measured in amplitude-modulation atomic force microscopy are discussed. Hysteresis in the interaction forces is shown to modify the dynamics of the cantilever leading to different power dissipation curves in the repulsive and attractive regimes. Experimental results together with numerical simulations show that power dissipati...

Understanding the power dissipation behavior of an application/workload is the key to writing power-efficient software and designing energy-efficient computer systems. Power modeling based on performance monitoring counters (PMCs) is an effective approach to analyze and quantify power dissipation behaviors on a real computer system. One of the potential benefits is that software developers are ...