Over the last decade, research in Electronic System Level (ESL) design has resulted in significant advances in addressing the rising design complexity and meeting the required performance constraints. Now a major concern of system-level design is the power reduction and energy dissipation of the system-on-chip which not only affects battery lifetime but also thermal aspects and reliability of t...

With the emergence of portable products as major players in the electronics market, controlling the power dissipation of integrated circuits is gaining increased importance. While progress is being made in improved battery technology to supply a larger amount of power per unit weight of the battery, it must also be coupled with an accompanying reduction in the power dissipation of IC's. Even fo...

A circuit design for a new high speed and Low Power 4-bit Braun Multiplier is presented. The multiplier is implemented by using different power reduction techniques. To design a multiplier it is necessary to design an AND gate and Full Adder circuit using the power reduction techniques is presented. The design uses CMOS digital circuits in order to reduce the power dissipation while maintaining...

A method to reduce the power dissipated by PLAs is presented in [3]. This method is addressing both static and dynamic PLAs. The objective is to minimize the number of literals and product terms of a logic function. However, [3] concluded that the static power dissipation of the NOR gates is the dominant power dissipation, and the optimization proposed cannot decrease significantly the power di...

Multiplier is the most basic unit of any electronic hardware whether it is microprocessor in cell phone or any DSP’s processors for signal processing. So power dissipation by multiplier is the most important parameter which is needed to be taken care of. So a lot of researches have been made till now and lot of efforts has been made to decrease the power consumption of this basic unit. From las...

A rapid growth in semiconductor technology and increasing demand for portable devices powered up by battery has led the manufacturers to scale down the feature size, resulting reduced threshold voltage and thereby enabling integration of extremely complex functionality on a single chip. In CMOS circuits, increased sub-threshold leakage current refers static power dissipation is the result of lo...

This paper reviews different encoding schemes for reduction of power dissipation, crosstalk noise and delay. Crosstalk is aggravated by enhanced switching activity which is often main cause for the malfunctioning of any VLSI chip. Consequently, delay and power dissipation also increases due to enhanced crosstalk. Reduction in switching activities through coupled transmission line results in eno...

In this paper we propose a coding scheme for general-purpose applications that can reduce power dissipation, crosstalk noise and crosstalk delay on the bus lines while simultaneously detecting errors at run time. The reduction in power dissipation can be achieved through reducing the bus switching activity. Not only is the switching activity in individual lines reduced but so is the coupling ac...

This paper explores the role of branch predictor organization in power/energy/performance tradeoffs for processor design. We find that as a general rule, to reduce overall energy consumption in the processor it is worthwhile to spend more power in the branch predictor if this results in more accurate predictions that improve running time. Two techniques, however, provide substantial reductions ...

This paper presents a broadband high operating frequency divide-by-2 frequency divider. This divider uses sourcecoupled logic (SCL) with two static loading master-slave D latches which achieves high input operating frequency, high input sensitivity and low power dissipation. This divider can work from 8GHz~ 27GHz and the input power is -40dBm@18GHz. The chip area is 735μm×480μm with only 4.6mW ...