One of the principal economic drivers for the semiconductor industry is high performance, low power applications for the portable electronics consumer market. Unfortunately, the power dissipation resulting from the use of conventional CMOS technology in this area is becoming a critical design issue. Supply voltage reduction has been the preferred technique for reducing power dissipation. Howeve...

Abstact: In on-chip buses, the RC crosstalk effect leads to serious problems, such as wire propagation delay and dynamic power dissipation. Crosstalk noise is dominated by the coupling capacitance, resulting in wire propagation delay, logical malfunction and power dissipation on on-chip buses. Therefore, eliminating crosstalk effects have become a very important consideration in the development...

CPU’s share, in overall power consumption, in a real-time system, is non-negligible. To reduce the power consumption of overall system, reduction in CPU power can be great advantage. Saving power in CPU can also advent for achieving lower operating temperature. In this writing, we show way for reducing power dissipation in CPU. The power dissipation in CPU is roughly proportional to the number ...

In this paper, we develop a novel technique based on Markov chains to accurately estimate power sensitivities to primary inputs in CMOS sequential circuits. A key application of power sensitivities is to construct a complicated power surface in the specification-space so as to easily obtain the power dissipation under any distribution of primary inputs, thereby offering an effective power macro...

The power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high compatibility of VLSI systems used in various applications, the power dissipation in CMOS circuits arises from it’s switching activity ,which is influenced by the supply voltage and effective capacitance. The power dissipation can be reduced by adopting different design style. Adiabatic logic s...

This paper describes a new technique for minimising power dissipation in full scan sequential circuits during test application. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by reducing spurious transitions during test application. The reduction is achieved by freezing the primary input part of the test vector u...