Fast low power SRAMs are becoming the critical component of many VLSI chips. There is increasing divergence in the speed of the processors and the main memory, and the power dissipation is also increasing due to increase in the integration and the operating speed as well as increase in the battery powered devices. The SRAM helps in bridging the gap and also reducing the power dissipation [1]. A...

In modern design ows low power aspects should be considered as early as possible to minimize power dissipation in the resulting circuit. A new BDD-based design style that considers switching activity optimization using temporal correlation information is presented. The technique is developed as an approximation method for switching activity estimation. Experimental results on a set of MCNC and ...

Now a day’s technology enhancement is at a blistering pace. Merely VLSI has a meteoric rise due to the adoption of new techniques. Static CMOS had a limitation of deploying constant power supply. Less power dissipation is an essential attribute for any optimized design. Varying the power supply is the very thing for preventing the power dissipation. An adiabatic logic is a new technique to redu...

In this paper we analyze the power consumption of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test because of the predictable addressing sequence. We exploit this observation in order to minimize power dissipation during test by eliminating the unnecessary power consumption associated with the pre-charge activity. This is achieved through a...

The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today’s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the long-term reliability of circuits...

For a significant number of electronic systems used in safety-critical applications circuit testing is performed periodically. For these systems, power dissipation due to BuiltIn Self Test (BIST) can represent a significant percentage of the overall power dissipation. One possible solution to address this problem consists of test pattern reordering with the purpose of reducing the amount of pow...

In this paper, a power macro-modelling technique at register transfer level (RTL) for the digital electronic systems composed of intellectual property (IP) components by using the statistical knowledge of their primary inputs/output is presented. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo ze...

Memories are a core part of most of the electronic systems. Performance in terms of speed and power dissipation is the major areas of concern in today’s memory technology. In this paper SRAM cells based on 6T, 7T, 8T, and 9T configurations are compared on the basis of performance for read and write operations. Studied results show that the power dissipation in 7T SRAM cell is least among other ...