Power dissipation during test is a significant problem as the size and complexity of systems-onchip (SOCs) continue to grow. During scan shifting, more transitions occur in the flip-flops compared to what occurs during normal functional operation. This problem is further pseudorandom filling of the unassigned input values is employed. Excessive power dissipation during test can increase manufac...

This paper presents a new adiabatic circuit technique called Positive Feedback Adiabatic Logic (PFAL). Power reduction is achieved by recovering the energy in the recovery phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. The main objective of this paper is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. The dy...

As transistors continue to scale down into the nanometer regime,device leakage currents are becoming the dominant cause of powerdissipation in nanometer caches, making it essential to model theseleakage effects properly. Moreover, typical microprocessor cachesare pipelined to keep up with the speed of the processor, and theeffects of pipelining overhead need to be proper...

This paper provides the estimation of power dissipation of CMOS and finFET based 6T SRAM Memory. CMOS expertise feature size and threshold voltage have been scaling down for decades for achieving high density and high performance. The continuing reduce in the feature size and the corresponding increases in chip density and operating frequency have made power consumption a major concern in VLSI ...

Our contribution in this paper is e3D, a diffusion based routing protocol that prolongs the system lifetime, evenly distributes the power dissipation throughout the network, and incurs minimal overhead for synchronizing communication. We compare e3D with other algorithms in terms of system lifetime, power dissipation distribution, cost of synchronization, and simplicity of the algorithm.

i ABSTRACT Nowadays transducers are ubiquitous as interfaces between the increasingly digital world and the real physical world. The same holds for the power amplifiers driving them. This thesis focuses on the design and optimization of high-voltage class-D amplifiers, which are used for driving capacitive piezoelectric actuator loads in active vibration/noise control applications. The main obj...

Corresponding Author: Maurizio Palesi Department of Computer Science Engineering, KORE University, Italy Email: [email protected] Abstract: The routing algorithm used in a Network-on-Chip (NoC) has a strong impact on both the functional and non functional indices of the overall system. Traditionally, routing algorithms have been designed considering performance and cost as the main obj...

Power optimization is the major problem in digital circuit design. In this paper using MTCMOS and stack techniques are proposed. Multi threshold CMOS sleep stack and logic stack, super cutoff sleep stack and logic stack are proposed. Stacking is introduced in MTCMOS concept which decreases leakage power based on the power dissipation of pMOS and nMO Stransistor. MTCMOS technique uses multiple v...

In digital VLSI, power dissipation has become a prime constraint. Many design architecture and techniques have been developed to reduce power dissipation. In this paper implementation of sequential circuits such as D flip flop, PIPO shift register and RAM in Gate diffusion input (GDI) technique and its comparison with other logic styles is presented. This technique allows reduced power consumpt...