This paper presents a hybrid CMOS-CNFET voltage controlled oscillator (VCO) with low power dissipation and linear response over a wide control voltage range. The hybrid circuit is based on PTM 32nm low power CMOS devices and 32nm CNFET devices with different threshold voltages. The VCO frequency and power dissipation are investigated for CNFET parameters such as number of nano-tubes, gate oxide...

Power dissipation is rapidly becoming a major design concern for companies in the high-end microprocessor market. The problem now is that designers are reaching the limits of circuit and mechanical techniques for reducing power dissipation. Hence, we must turn our attention to architectural approaches to solving this problem. In this work we propose a method of instruction scheduling which limi...

A 2.4-GHz single-stage CMOS low noise amplifier (LNA) structure with ultra low power consumption is proposed. A current reuse technique is used to decrease power dissipation with increasing amplifier transconductance for the LNA. Thus, the same amplifier transconductance for the LNA will be achieved at decreased power dissipation. Also, due to the use of an inverter-type amplifier which has a s...

In large chips, the propagation delay of the data and clock signals can limit performance due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current. In order to develop a repeater design methodology, a timing model characterizing a complementa...

Digital multipliers are a major source power dissipation in digital signal processors. Array architecture is a popular technique to implement these multipliers due to its regular compact structure. High power dissipation in these structures is mainly due to the switching of a large number of gates during multiplication. In addition, much power is also dissipated due to a large number of spuriou...

The "system-on-chip" revolution has posed a number of new challenges to the test engineers. We address the issue of high power dissipation during testing, which can reach levels that are beyond the safe upper limit associated with the chosen packaging technology. A study undertaken by Zorian reveals that test power can be as large as 200% or more in comparison to the normal power. In the test m...

A balance between static and dynamic losses of a power MOSFET is always desirable for accomplishing the maximum efficiency specific converter. The standard semiconductor theory suggests that minimum dissipation in can be achieved by selecting device active area. However, circuit designers, area unknown given only datasheet parameters are available. Hence, this paper, we propose simple method, b...

It has been shown [2] that adiabatic switching can significantly reduce the dynamic power dissipation in an integrated circuit. Due to the overhead in the realization of adiabatic logic blocks [3] the best results are achieved when it is used only for charging dominant loads in an integrated circuit [7]. It has been demonstrated [4] that a multi stage driver is needed for minimal power dissipat...

It has been shown (Athas et al., 1994) that adiabatic switching can significantly reduce the dynamic power dissipation in an integrated circuit. Due to the overhead in the realization of adiabatic logic blocks (Saas et al., 2000) the best results are achieved when it is used only for charging dominant loads in an integrated circuit (Voss and Glessner, 2001). It has been demonstrated (Saas et al...