Power consumption is an increasingly important issue in general purpose processors, particularly in the mobile computing segment. In present processors, most of the power dissipation is dynamic power dissipation, which arises due to signal transitions. Various techniques have been studied and implemented to reduce dynamic power dissipation, including clock gating, cache sub-banking, voltage sca...

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing shortcircuit current by a piece-wise linear function and considering a current owing from input node to output node through gate capacitances, the accuracy is improved signi cantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experime...

Main source of power dissipation for dynamic CMOS circuits is due to charging and discharging of intrinsic capacitances, commonly referred to as switching power. As switching power dissipation is proportional to the square of supply voltage, lowering the supply voltage is the most effective way to reduce switching power dissipation. However, the reduction of switching power by lowering the supp...

This paper addresses the issues of power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimizing short circuit power and subthreshold leakage power which is predominant when supply voltage (VDD) and threshold volt...

Static power dissipation is increases with the scaling in threshold voltage and expected to become important part of total power consumption. In the present work, a new configuration of level shifters for low power application in 0.25μm technology has been presented. The proposed circuits utilize the merit of stacking technique by which there is reduction in leakage power. In this work a new le...

This study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation...

We propose a hybrid power model for estimating the power dissipation of a design at the RT-level. This new model combines the advantages of both RT-level and gate-level approaches. We investigate the relationship between steadystate transition power and overall power dissipation. We observe that, statistically, two input sequences causing similar amount of steady-state transitions will exhibit ...

In present scenario, an increasing demand for mobile electronic devices such as cellular phones, laptop computers and personal digital assistants requires the use of power efficient circuits. To minimize the power dissipation and to increase the battery lifetime, the supply voltage, VDD has been scaled down continuously. So, scaling down the supply voltage, without scaling down the threshold vo...

Power dissipation as a measure of peripheral resistance in vascular networks

In this paper, we suggest that the dynamic power dissipation of a circuit can be used to detect faults in it. The change in dissipation caused by a fault can be maximized by applying speciic test vectors. For example circuits, we show that the power dissipation can be used to detect faults which do not aaect static power dissipation. We also discuss how faults may be detected with a frequency d...