Traditional DFT methodologies increase useless power dissipation during testing and are not suitable for testing low power VLSI circuits leading to lower reliability and manufacturing yield. Traditional test scheduling approaches based on fixed test resource allocation decrease power dissipation at the expense of higher test application time. On the one hand it was shown that power conscious te...

We present a method for power and delay optimization by input reordering. We observe that the reordering has a significant effect on the power dissipation of the gate which drives the reordered gate. This is because the input capacitance depends on the signal values of other inputs. This property, however, has not been utilized for power reduction. Previous approaches focus on the reduction of ...

It is noted that the results of recent experiments on the enhancement of turbulent kinetic energy (TKE) dissipation below surface waves can be stated as follows. TKE dissipation is enhanced by a factor 15Hws/z at depths 0.5Hws < z < 20Hws with respect to the wall-layer result ǫ = u ∗w/κz, where u∗w is the friction velocity in water and Hws is the significant windsea wave height. For open ocean ...

Conventional MOS models for circuit simulation assume that the channel capacitances do not contribute to net power dissipation. Numerical integration of channel currents and instantaneous terminal voltages however shows the existence of higher order dissipating terms. To overcome these limitations, we present a self-consistent, first order, quasi-static power dissipation model that is able to p...

In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literatu...

This paper reviews architectural and circuit design considerations for realization of low power dissipation in high-speed CMOS A/D converters. Basic limitations on achievable power dissipation in MOS samplers and quantizers is first discussed. Then a number of practical design aspects are illustrated with discussion of a 10-bit, 20-Msample/s pipeline A/D converter[1] implemented in 1.2-μm CMOS ...

Gate-sizing is an effective technique to optimize CMOS circuits for dynamic power dissipation and performance while dual-V,h (threshold voltage) CMOS is ideal for leakage power reduction in low voltage circuits. This paper focuses on simultaneous dual-V,h assignment and gate-sizing t o minimize the total power dissipation while maintaining high performance. An accurate power dissipation model t...

The fast growth of the power density in integrated circuits has made area and power dissipation as the vital design measures. In this paper, several different flip-flop topologies are analyzed and an area, power efficient flip-flop design is proposed. This design overcomes the power dissipation due to the large precharge node capacitance, with reduced number of transistors. The comparative powe...

Abstract: In this paper, a power-gating technology for single-rail MOS Current Mode Logic (SRMCML) circuits is presented, which use the high-threshold PMOS transistors as linear load resistors to reduce the power dissipation in the sleep mode. The basic SRMCML cells, such as buffer/inverter, AND2/NAND2, AND3/NAND3, OR2/NOR2, OR3/NOR3, XOR2/XNOR2, multiplexer, and 1-bit full adder, are used to v...