This paper presents Swift, a packet filter for high performance packet capture on commercial off-the-shelf hardware. The key features of Swift include (1) extremely low filter update latency for dynamic packet filtering, and (2) Gbps high-speed packet processing. Based on complex instruction set computer (CISC) instruction set architecture (ISA), Swift achieves the former with an instruction se...

We present a high performance implementation of the FFT algorithm on the BOPS ManArray parallel DSP processor. The ManArray we consider for this application consists of an array controller and 2 to 4 fully interconnected processing elements. To expose the parallelism inherent to an FFT algorithm we use a factorization of the DFT matrix in Kronecker products, permutation and diagonal matrices. O...

Prompted by the recent shift of attention from just focusing on the top-down processing in L2 reading towards considering the basic component, bottom-up processing, the role of phonological component has also enjoyed popularity among a selected circle of SLA investigators (Koda, 2005). This study investigated the effect of the automatization of the phonological component on the reading comprehe...

Prior expectations influence the way incoming stimuli are processed. A standard, validated way of manipulating prior expectations is to bias participants to perceive a stimulus by instructing them to look out for this type of stimulus. Here, we investigated the influence of prior expectations on the processing of incoming stimuli (emotional faces) in adolescence. Using functional magnetic reson...

this study investigates and compares the efficacy of differentiated instruction and traditional-based instruction on enhancing iranian students’ reading comprehension. eight elementary, intermediate, and advanced classrooms from 1 language institute were chosen, and based on their performance on the pretests were further divided into 4 control and 4 treatment groups. flexible grouping, tiered i...

Performing multiple, accurate, low-latency predictions is crucial to improving instruction throughput in future wide-issue microprocessors. However, demands of wide-issue processing coupled with implementation challenges posed by high clock frequencies present obstacles to these prediction goals. This paper proposes the Traveling Speculation framework to accommodate predictions in a wide-issue ...

This paper presents an approach to scheduling loops that leverages the distinctive architectural features of the XIMD, particularly the variable number of instruction streams and low synchronization cost. The classical VLIW and MIMD architectures have a fixed number of instruction streams, each with a fixed width. A compiler for the XIMD architecture can exploit fine-grained parallelism within ...

Scientific computations for diffusion equations and ANNs (Artificial Neural Networks) are data intensive tasks accompanied by heavy memory access; on the other hand, their computational complexities are relatively low. Thus, this type of tasks naturally maps onto SIMD (Single Instruction Multiple Data stream) parallel processing with distributed memory. This paper proposes a high performance ac...

Embedded security devices like ‘Trusted Platforms’ require both scalability (of power, performance and area) and flexibility (of software and countermeasures). This thesis illustrates how data parallel techniques can be used to implement scalable architectures for cryptography. Vector processing is used to provide high performance, power efficient and scalable processors. A programmable vector ...

Superscalar processing is the latest in a long series of innovations aimed at producing ever-faster microprocessors. By exploiting instruction-level parallelism, superscalar processors are capable of executing more than one instruction in a clock cycle. This paper discusses the microarchitecture of superscalar processors. We begin with a discussion of the general problem solved by superscalar p...