Proper use of native signal processing (NSP) instruction set enhancements can result in speedup for targeted applications. In this paper, we study the behavior of the X86 architecture's Multimedia Extension (MMX) instruction set on signal processing and multimedia algorithms and applications. In addition to quantifying speedup, we make comparisons based on detailed dynamic instruction pro ling....

The present study tracked activation pattern differences in response to sign language processing by late hearing second language learners of American Sign Language. Learners were scanned before the start of their language courses. They were scanned again after their first semester of instruction and their second, for a total of 10 months of instruction. The study aimed to characterize modality-...

Objective: The goal of this project is to evaluate the effectiveness of two different techniques for exploiting the Instruction Level Parallelism (ILP) available in Digital Signal Processing (DSP) and Multimedia applications. VLIW (Very Long Instruction Word) architectures have multiple functional units to take advantage of such a parallelism, while the SIMD (Single Instruction Multiple Data) a...

Three dimensional (3D) graphics applications is an important workload running on today’s computer system. A cost-effective graphics solution is to use a general processor for 3D geometry processing and a specialized hardware for rasterization. 3D geometry processing is an inherently parallel task. Therefore, many CPU vendors add SIMD (Single Instruction Multiple Data) instruction extensions to ...

This study explored the effect of input vs. collaborative output tasks on Iranian EFL learners’ grammatical accuracy and their willingness to communicate (WTC). In so doing, the study utilized 3 input (i.e., textual enhancement, processing instruction, and discourse) and 3 collaborative output (i.e., dictogloss, reconstruction cloze task, and jigsaw) tasks and compared their effects on 5 Englis...

In this paper we introduce the Delft-Java multithreaded processor architecture and organization. The proposed architecture provides direct translation capability from the Java Virtual Machine instruction set into the Delft-Java instruction set. The instruction set is a 32-bit RISC instruction set architecture with support for multiple concurrent threads and Java speci c constructs. The parallel...

Extensible processors are application-specific instruction set processors (ASIPs) that allow for customisation through user-defined instruction set extensions (ISE) implemented in an extended micro architecture. Traditional design flows for ISE typically involve a large number of different tools for processing of the target application written in C, ISE identification, generation, optimisation ...

Digital signal processors with Harvard architecture are being gradually replaced by digital signal processors with VLIW (Very Long Instruction Word) architecture for high-end applications. Owing to exploiting the principles of parallel instruction processing and parallel data processing, the new architecture provides the calculation power to implement complex algorithms of digital signal proces...

To provide flexibility in deploying new protocols and services, general-purpose processing engines are being placed in the datapath of routers. Such network processors (NPs) are typically simple RISC multiprocessors that perform forwarding and custom application processing of packets. The inherent unpredictability of execution time of arbitrary instruction code poses a significant challenge in ...