In this paper we propose a blocking-aware partitioning algorithm which allocates a task set on a multiprocessor (multi-core) platform in a way that the overall amount of blocking times of tasks are decreased. The algorithm reduces the total utilization which, in turn, has the potential to decrease the total number of required processors (cores). In this paper we evaluate our algorithm and compa...

Banyan networks are being proposed for interconnecting memory and processor modules in multiprocessor systems as well as for packet switching in communication networks. This paper describes an analysis of the performance of a packet switch based on a single-buffered Banyan network. A model of a single-buffered Banyan network provides results on the throughput, delay, and internal blocking. Resu...

This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digital signal processor (DSP) architecture is to use complex organizations to exploit instruction level parallelism (ILP). The two most common approaches for exploiting the ILP are Superscalars and Very Long Instruction Wo...

In block-partitioned parallel matrix factorization algorithms, where the matrix is distributed over a logical torus processor grid with an rs block-cyclic matrix distribution, the greatest scope for optimization exists in the formation of (block) panels. Let ! be the panel width, with ! m being an optimal value based on the characteristics a single processor's memory hierarchy. To date, two wel...

to compare intubating conditions and hemodynamic changes between bonfils intubation fiberscope and macintosh laryngoscopy without administering neuromuscular blocking drugs (nmbds). methods: in this randomized controlled trial,80 male and female patients, scheduled for elective surgery, aged 15 to 60 years, asa class ii or i, non-obese, non smokers, without anticipated difficult intubation; wer...

This paper explores collective personalized communication. For example, in all-to-all personalized communication (AAPC), each processor sends a distinct message to every other processor. However, for many applications, the collective communication pattern is many-to-many, where each processor sends a distinct message to a subset of processors. In this paper we first present strategies that redu...

Existing multiprocessor synchronization mechanisms are relatively heavyweight, due in part to the level of the memory hierarchy (typically main memory) at which threads must synchronize. Multithreaded processors, on the other hand, have the potential to significantly reduce synchronization cost, because threads share the processor simultaneously and can synchronize using processor-internal stat...

As mobile computing is getting popular, there is an increasing interest in techniques that can minimize energy consumption and prolong the battery life on mobile devices. Processor voltage scheduling is an effective way to reduce energy dissipation by reducing the processor speed. In this paper, we study voltage scheduling for real-time periodic tasks with non-preemptible sections. Three scheme...

This thesis describes and evaluates the effectiveness of four hardware mechanisms for software shared memory: block status bits, a global translation lookaside buffer, a fast, non-blocking, event system, and dedicated thread slots for software handlers. These mechanisms have been integrated into the M-Machine's MAP processor, and accelerate tasks which are common to many shared-memory protocols...

We investigate the relative performance impact of nonblocking loads, stream buffers, and specula five execution both used individually and in conjunction with each other. We have simulated the SPEC92 benchmarks on a statically scheduled quad-issue processor model. running code from the Multijlow compiler. Non-blocking loads and stream buffers both provide a signif cant performance advantage, an...