Widespread use of multi-core systems demand highly parallel applications and algorithms in everyday computing. Parallel data structures, which are basic building blocks of concurrent algorithms, are hard to design in a way that they remain both fast and simple. By using mutual exclusion they can be implemented with little effort, but blocking synchronization has many unfavorable properties, suc...

In this paper we provide both a qualitative and a quantitative evaluation of a decoupled multithreaded architecture that uses non-blocking threads. Our architecture is based on simple in-order pipelines and complete decoupling of memory accesses from execution pipelines. We extend the architecture to support thread level speculation using snooping cache coherency protocols. We evaluate the perf...

We develop an efficient parallel distributed algorithm for matrix completion, named NOMAD (Non-locking, stOchastic Multi-machine algorithm for Asynchronous and Decentralized matrix completion). NOMAD is a decentralized algorithm with non-blocking communication between processors. One of the key features of NOMAD is that the ownership of a variable is asynchronously transferred between processor...

Most multiprocessors are multiprogrammed in order to achieve acceptable response time and to increase utilization. Unfortunately, inopportune preemption may significantly degrade the performance of synchronized parallel applications. To address this problem, researchers have developed two principal strategies for concurrent, atomic update of shared data structures: preemption-safe locking and n...

the above equation, we can see that we will get the best performance if we choose a blocking factor that is a multiple of 3. In general, the theorem implies that there are only blocking factors to consider; this characterizes the critical path for all unfoldings greater than. In this paper, we have developed a formulation for the problem of finding optimal blocking factors for blocked, non-over...

The convergence of highly parallel many-core graphics processors with conventional multi-core processors is becoming a reality. To allow algorithms and data structures to scale efficiently on these new platforms, several important factors needs to be considered. (i) The algorithmic design needs to utilize the inherent parallelism of the problem at hand. Sorting, which is one of the classic comp...

Future systems for multi-core architectures will have to be highly parallelizable to utilize hardware and will have to avoid sharing to achieve good performance. Consequently, novel operating system designs gradually move towards asynchronous message-based communication and decentralized scheduling. In this paper we describe a message passing and scheduling architecture which provides main comm...

Most embedded systems are designed to perform one or fewer specific functions. It is important that the hardware and the software must closely interact to achieve maximum efficiency in all of these realms and overcome the drawbacks found in each aspect. This research focuses on designing a totally new Instruction Set Architecture (ISA) as well as hardware that can closely tie together with the ...

Abstract Here, a move blocking (MB) based direct voltage model predictive control (DVMPC) strategy is introduced to enhance the dynamic performance of DC microgrid in presence constant power loads (CPLs). For this aim, an automatic discrete first developed for boost converter. Considering CPL effects on converter, then designed directly regulate output Move finally integrated into DVMPC order e...

In a previous work it was shown that the performance of linear algebra computations , which access large amounts of data, is dependent on the behavior of the memory hierarchy. This research is aimed to use the multilevel orthogonal blocking approach in conjuntion with other software techniques to further improve the performance of linear algebra computations. The performance of the dense matrix...