Arrays in behavioral specifications that are too large to fit into on-chip registers are usually mapped to off-chip memories during behavioral synthesis. We address the problem of system power reduction through transition count minimization on the memory address bus when these arrays are accessed from memory. We exploit regularity and spatial locality in the memory accesses and determine the ma...

Current trend of technology scaling makes it possible to put a huge number of transistors on a single die. While dynamic power consumption can benefit from technology scaling, static power consumption get worse, thus making the latter the dominant factor of power consumption in future microprocessor systems. As on-chip cache memories require the most part of chip area and number of transistors,...

In this research, the radical scavenging activity and reducing power of the ethyl acetate fraction and subfractions of Salvia mirzayanii (SM) have been investigated. The plant material was initially extracted with ethanol. The fractionation was carried out using liquid-liquid extraction, then the ethyl acetate fraction, which showed the greatest antioxidant activity, was selected. This fraction...

A novel approach for minimizing power during scan testing is presented. The idea is that given a full scan module or core that has multiple scan chains, the test set is generated and ordered in such a way that some of the scan chains can have their clock disabled for portions of the test set. Disabling the clock prevents flip-flops from transitioning, and hence reduces switching activity in the...

D riven by changing reimbursement models, the rapidly changing science of medicine and increasing competitive pressures on health systems, enterprise-level analytics is critical for healthcare organizations. Historically, health systems have approached analytics primarily from an incremental, retrospective and operational-siloed approach. This approach, " Analytics 1.0, " has historically labor...

With the increased clock frequency of modern, high-performance processors (over 500 MHz, in some cases), limiting the power dissipation has become the most stringent design target. It is thus mandatory for processor engineers to resort to a large variety of optimization techniques to reduce the power requirements in the hot zones of the chip. In this paper, we focus on the power dissipated by t...

The need for low power dissipation in portable computing and wireless communication is making design communities accept ultra low voltage CMOS processes. With the lowering of' supply voltage, the transistor thresholds (Vth) have to be scaled down to meet the performance requirements. However, such scaling can increase the leakage current through a transistor, thereby increasing the leakage powe...