This paper studies interconnect delay and area estimation for multiple-pin nets with consideration of interconnect optimizations, including optimal wire sizing (OWS), and simultaneous bu er insertion/sizing and wire sizing (BISWS), under two types of optimization objectives: one is to minimize delay to a single critical sink, and the other is to minimize the maximum delay to all critical sinks....

This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. Since the delay under this mode...

Ensuring building-block (BB) mixing is critical to the success of genetic and evolutionary algorithms. This study develops facetwise models to predict the BB mixing time and the population sizing dictated by BB mixing for single-point crossover. The population-sizing model suggests that for moderate-to-large problems, BB mixing – instead of BB decision making and BB supply – bounds the populati...

This paper presents a new approach using simultaneous voltage-scaling and gate-sizing for low power without violating the timing constraints. We provide the problem formulation in this application, and propose algorithms for single voltagescaling, single gate-sizing, and their simultaneous manipulation. We target a globally optimal solution by showing how the power optimization is related to th...

This paper investigates the optimal sampling and the speed-up obtained through sampling for the sampled OneMax problem. Theoretical and experimental analyses are given for three different population-sizing models: the decision-making model, the gambler’s ruin model, and the fixed population-sizing model. The results suggest that, when the desired solution quality is fixed to a high value, the d...

We present a novel technique to automatically calculate an initial sizing of analog circuits that conforms to good design practice. The method is purely (DC) simulation-based and does not need symbolic design equations or user design knowledge. It identifies the space of feasible design parameters based on implicit specifications, which arise from the circuit topology. A sizing centered within ...

An interconnect joining a source and a sink is divided into xed length uniform width wire segments and some adjacent segments have bu ers in between The problem we considered is to simultaneously size the bu ers and the segments so that the Elmore delay from the source to the sink is minimized Previously no polynomial time al gorithm for the problem has been reported in literature In this paper...

This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for high-performance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the layout optimization. Then, we summarize the available performance optimization techniques for VL...

We consider the problem of determining realistic and easy-to-schedule lot sizes in a multiproduct, multistage manufacturing environment. We concentrate on a specific type of production, namely, flow shop type production. The model developed consists of two parts, lot sizing problem and scheduling problem. In lot sizing problem, we employ binary integer programming and determine reorder interval...

In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitance in a wire are included in interconnect delay calculation. Combined with general ASIC design flow, we construct section constraint graph in each routing region and use the graph to guide segment sizing and spacing. By ...