As soft errors are important design concerns in embedded systems, several schemes have been presented to protect systems against them. Embedded can be protected by hardware redundancy; however, hardware-based protections cannot provide flexible protection due hardware-only modifications. Further, they incur significant overheads terms of area, performance, and power consumption. Therefore, redu...

This work presents the evaluation of a new dual-core lockstep hybrid approach aimed to improve fault tolerance in microprocessors. Our takes advantage modern multicore processor resources combine software-based with custom hardware observer. The first is used duplicate data and instruction flows; meanwhile, second charge control-flow monitoring. proposal has been implemented ARM microprocessor ...

Validating or accessing the accuracy of soft classification maps has rapidly developed over the past few years. This assessment employs a soft error matrix as generalized from the traditional, hard classification error matrix. However, the impact of positional error on the soft classification is uncertain and whether the well-accepted half-pixel registration accuracy is suitable for the soft cl...

xxxvii Zusammenfassung der Arbeit xxxix The Big Picture behind the Thesis xliii

This paper describes a novel TCAM architecture designed for enhancing the soft-error immunity. An associated embedded DRAM and ECC circuits are placed next to TCAM macro to implement a unique methodology of recovering upset bits due to soft errors. The proposed configuration allows an improvement of soft-error immunity by 6 orders of magnitude compared with the conventional TCAM. We also propos...