Conventional full-custom reconfigurable logic device design and implementation are time consuming processes. In this research, we propose a design framework in order to improve FPGA IP core design efficiency by link academic FPGA design flow and commercial VLSI CADs based on the synthesizable method. A novel FPGA routing tool is developed in this framework, namely the EasyRouter. By using simpl...

A new VLSI design center VDEC spearheaded by Tokyo University and supported by the Japanese Government is about to alter the course of the microlectronic systems design education at Japanese Universities. The industrial support for microelectronic education and how a new and innovative Japanese University specializing in Computer Science and Computer Engineering uses projects in its curriculum ...

Preface In the past two decades, the fields of VLSI systems design and massively parallel computation have grown into mature disciplines. Both fields began as research topics in industrial and academic laboratories; today, they form the core technologies for several large corporations. This report proposes a massively parallel computer, the Connectionist Network Supercomputer (CNS-1), which lev...

Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits it is often essential to sub-divide a circuit into smaller parts.Circuit partitioning plays an important role in physical design automation of very large scale integration(VLSI)chips.In VLSI.In VLSI circuit partitioning the problem of obtaining minimum cut is of prime importance.To enhance other criter...

---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Floorplanning is an important problem in very large scale integrated-circuit (VLSI) design automation as it determines the performance, size, yield, and reliability of VLSI chips. From the computational point of view, VLSI floorplanning is an NP-ha...

This paper presents a new tool for the synthesis of low-power VLSI designs, specifically, those designs targeting digital signal processing applications. The synthesis tool genetic algorithm for low-power synthesis (GALOPS) uses a genetic algorithm to apply power-reducing transformations to high-level signal-processing designs, producing designs that satisfy power requirements as well as timing...

In recent, asynchronous design has been resurged to exploit potential advantages of asynchronous VLSI such as; high-performance, low power consumption, timing fault tolerance and design cost reduction. This paper describes our first design and implementation of DINAMIK project which aims to show realizability of potential merits of asynchronous VLSI and to establish the design methodology. In t...

The question raised by the panel is how much testing should be included in a VLSI Design course and what makes a “well-rounded” electrical and computer engineering graduate. The fact that we had to have a National Science Foundation workshop and now an ITC panel to discuss how to incorporate test in a design course shows that the disconnect between design and test happens not only in industry b...

Power consumption plays an essential role in VLSI design. Earlier, the VLSI designers were more concentrated on performance and area, but, gradually, low power consumption became one of the most important factors in VLSI design. Increasing demand and growth of portable devices have increased the demand of power efficient VLSI circuits. In this paper, various conventional low power designs are a...

In this paper, we present an efficient circulant approximation based MIMO equalizer architecture for the CDMA downlink. This reduces the Direct-Matrix-Inverse (DMI) of size (NF × NF ) with O((NF )3) complexity to some FFT operations with O(NF log2(F )) complexity and the inverse of some (N × N) sub-matrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization a...