Reconfigurable devices have potential for great flexibility/efficiency, but mapping algorithms onto these architectures is a long-standing challenge. This paper addresses this challenge for stripe based coarse-grained reconfigurable architectures (CGRAs) by drawing on insights from graph drawing. We adapt fast, iterative algorithms from hierarchical graph drawing to the problem of mapping to st...

In this paper, we consider spatial networks that realize a balance between an infrastructure cost (the cost of wire needed to connect the network in space) and communication efficiency, measured by average shortest path length. A global optimization procedure yields network topologies in which this balance is optimized. These are compared with network topologies generated by a competitive proce...

Placement process is one of the vital stages in physical design. In this stage, modules and elements of circuit are placed in distinct locations according to optimization basis. So that, each placement process tries to influence on one or more optimization factor. In the other hand, it can be told unequivocally that FPGA is one of the most important and applicable devices in our electronic worl...

Hierarchical interconnection networks provide high performance at low cost by exploring the locality that exists in the communication patterns of massively parallel computers. A Symmetric Tori connected Torus Network (STTN) is a 2D-torus network of multiple basic modules, in which the basic modules are 2D-torus networks that are hierarchically interconnected for higher-level networks. We also f...

The STM tunneling through a quantum wire (QW) with a side-attached impurity (atom, island) is investigated using a tight-binding model and the nonequilibrium Keldysh Green function method. The impurity can be coupled to one or more QW atoms. The presence of the impurity strongly modifies the local density of states of the wire atoms, thus influences the STM tunneling through all the wire atoms....

In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitance in a wire are included in interconnect delay calculation. Combined with general ASIC design flow, we construct section constraint graph in each routing region and use the graph to guide segment sizing and spacing. By ...

We propose a provably good performance-driven global routing algorithm for both cell-based and building-block design. The approach is based on a new bounded-radius minimum routing tree formulation. We first present several heuristics with good performance, based on an analog of Prim's minimum spanning tree construction. Next, we give an algorithm which simultaneously minimizes both routing cost...

BACKGROUND Unstable steel wire cerclage following open heart surgery may result in increased pain, sternal cut-through, non-union, or dehiscence. These complications lead to longer hospital stays, increased cost, higher morbidity, and patient dissatisfaction. The Figure 8 FlatWire Sternal Closure System is a new construct which is a simple, intuitive, and inexpensive alternative for primary ste...

We report here on a theoretical model for the electronic structure and transport properties of superlattice nanowires, considering their cylindrical wire boundary and multiple anisotropic carrier pockets. The thermoelectric properties of superlattice nanowires made of various lead salts ~PbS, PbSe, and PbTe! are investigated as a function of the segment length, wire diameter, crystal orientatio...

The boundaries of oral lesions in color images were detected using a live-wire method and compared to expert delineations. Multiple cost terms were analyzed for their inclusion in the final total cost function including color gradient magnitude, color gradient direction, Canny edge detection, and Laplacian zero crossing. The gradient magnitude and direction cost terms were implemented so that t...