Issues concerning the accuracy of hot-wire measurements in turbulent pipe flow are addressed for pipe Reynolds numbers up to 6 × 106 and hot-wire Reynolds numbers up to Rew ≈ 250. These include the optimization of spatial and temporal resolution and the associated feature of signal-to-noise ratio. Very high wire Reynolds numbers enable the use of wires with reduced length-to-diameter ratios com...

Wire length minimization ( W L M ) has received szgnificant attention in the compaction stage of VLSI layout synthesis. In most cases, reduction in wire length also results in better circuit yield. However, a trade-off may stall exist between total wire length and yield. In WLM only the area/length of the layout patterns is considered whereas for yield enhancement both the area of the layout pa...

Double-twisted hexagonal gabion wire mesh is a type of reinforced soil material that used in retaining walls to stabilize the slope geotechnical engineering. In this study, series tensile tests were conducted investigate behavior mesh. Meanwhile, numerical models built whole loading-strain process. The influence diameter, width, and length on strength evaluated based laboratory simulation. quan...

We introduce wire length as a salient complexity measure for analyzing the circuit complexity of sensory processing in biological neural systems. This new complexity measure is applied in this paper to two basic computational problems that arise in translationand scale-invariant pattern recognition, and hence appear to be useful as benchmark problems for sensory processing. We present new circu...

The Hotelling's  control chart, is the most widely used multivariate procedure for monitoring  two or more related quality characteristics, but it’s power lacks the desired performance in detecting small to moderate shifts. Recently, the variable sampling intervals (VSI) control scheme in which the length of successive sampling intervals is determined upon the preceding values has been proved t...

We would like to thank the authors of 15] for providing V4R routing solutions and sharing the information of the V4R via counting procedure. We would like to thank Randall Helzerman for proofreading our manuscripts. 15 For the layer assignment problem in VLSI layout, we can always represent the penalties for connict and discontinuity using a cost matrix for each edge. We assume we have the cost...

Minimizing clock skew is a very important problem in the design of high performance VLSI systems. We present a general clock routing scheme that achieves extremely small clock skews, while still using a reasonable amount of wire length. This routing solution is based on the construction of a binary tree using recursive geometric mat thing. We show that in the average case the total wire length ...

We first present a unged formulation to three problems in VLSI physical design: Layout compaction, Wire balancing and Integrated layout compaction and wire balancing problems. The aim of layout compaction is to achieve minimum chip width. Whereas wire balancing seeks to achieve minimum total wire length, integrated layout compaction and wire balancing seeks to minimize wire length maintaining t...