A 0.9 V wideband SPLL with an adaptive fast‐locking circuit achieving 24.68 µs settling time reduction
نویسندگان
چکیده
A low-power wideband self-biased phase-locked loop (SPLL) is proposed for multi-protocol SerDes applications in this letter. With the adaptive fast-locking current circuit (AFLCC) and charge pump (CP), settling time reduced significantly, no extra power jitter contribution. In addition, a start-up module adopted to reset system an optimal initial operating frequency quickly. The 1-3-GHz SPLL, fabricated TSMC 28-nm CMOS process, occupies compact 0.028 mm2 area. It achieves roughly constant of 5 μs over all frequencies division ratios range. Only 0.96 mW consumed at 1 GHz frequency.
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ژورنال
عنوان ژورنال: Electronics Letters
سال: 2023
ISSN: ['0013-5194', '1350-911X']
DOI: https://doi.org/10.1049/ell2.12862