A 12.5-Gb/s Low Power Receiver with Equalizer Adaptation

Low - Power Turbo Equalizer Architecture

In this paper, we propose a low complexity architecture for turbo equalizers. Turbo equalizers jointly equalize and decode the received signal by exchanging soft information iteratively. The proposed architecture employs early termination of the iterative process when it does not impact the bit-error rate PER). Early termination enables the powering down parts of the soft-input soft-output (SIS...

Low-Power Equalizer VLSI Implementation for xDSL

A Low - Power Architecture Forphase - Splitting Passband Equalizer 1

A low-power architecture for phase-splitting passband equalizer (PSPE) is proposed in this paper. Carrierless AM/PM (CAP) transmission scheme, which is a standard for numerous broadband communication systems including ATM-LAN networks, employs PSPE at the receiving end to combat channel distortion and crosstalk. The conventional PSPE requires two independent adaptive lters that form the in-phas...

A compact, low-power-consumption 5-Gbps OEIC receiver without equalizer fabricated in 0.18-µm CMOS technology

A low-cost, compact 5-Gbps fully integrated CMOS optical receiver without equalizer is fabricated in this paper in a standard 0.18-μm CMOS technology. The measured responsivity of the DNW-strip-SMPD operating in avalanche mode is 1.4A/W, while the bandwidth is 2.9GHz with 11.6V reverse bias voltage. The application for 5-Gbps very-short-reach optoelectronic integrated circuit (OEIC) receiver wi...

A 125 MHz Digital Equalizer for Broadband Communications

A 125 MHz digital equalizer has been designed based on a 0.25 μm CMOS standard cell library. Partially conforming to the Gigabit Ethernet 1000Base-T standard, the equalizer includes a 16-tap feed-forward adaptive FIR filters accepting 8-bit input, and a 16-tap decision-feedback adaptive FIR filters producing 5-level output symbols. The modified Booth encoding and Wallace tree compression scheme...