A cryogenic low power CMOS analog buffer at 4.2K
نویسندگان
چکیده
A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results simulation SMIC 0.18um CMOS technology show the high driving capability and low quiescent power consumption cryogenic temperature. Operating single 1.4 V supply, could a slew-rate +51 V/us -93 for 10 pF capacitive load. static only 79uW.
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2021
ISSN: ['1349-2543', '1349-9467']
DOI: https://doi.org/10.1587/elex.18.20210183