A Methodology for Constraint-Driven Synthesis of On-Chip Communications

A Methodology and an Open Software Infrastructure for Constraint-Driven Synthesis of On-Chip Communications

An SoC is modeled as a set of pre-designed cores characterized by their area and interfaces and a set of end-to-end communication requirements on the channels connecting them. These requirements are the input specification to a synthesis process that produces an on-chip communication (OCC) by assembling components such as interfaces, routers, buses and links, from a target library. Models for f...

A Time Driven Methodology for Key Dimensioning in Multicast Communications

A Constraint-Driven Placement Methodology for Analog Integrated Circuits

A new constraint-driven methodology for the placement of analog IC's is described. Electrical performance speciications are automatically translated into constraints on the layout parasitics. These constraints and the sensitivity information of the circuit are then used to control a Simulated Annealing-based placement algorithm. At each step of the annealing a fast check on performance degradat...

Chip-to-Chip and On-Chip Communications

In high-performance integrated circuits manufactured in CMOS deep sub-micron technology, the speed of global information exchange on the chip has developed into a bottleneck, that limits the effective information processing speed. This is caused by standard on-chip communication based on multi-conductor interconnects, e.g., implemented as parallel interconnect buses. The supported clock frequen...

Multiple-Constraint Driven System-on-Chip Test Time Optimization

The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. These complex chips include a high number of fault sites, which need a high test data volume for testing, and the high test data volume leads to long test application times. For modu...