A Model for Scalable and Balanced Accelerators for Graph Processing
نویسندگان
چکیده
Designing a graph processing system that can scale to sizes are orders of magnitude larger than what is possible on single accelerator requires careful codesign memory bandwidth and capacity, the interconnect between accelerators, overall architecture. We present high-level bottleneck-analysis model for design evaluation scalable balanced accelerators processing. show several applications this including how choose right mix different types, network topology, bisection bandwidth, system-level architecture match access patterns capacity requirements data structures given performance target.
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ژورنال
عنوان ژورنال: IEEE Computer Architecture Letters
سال: 2022
ISSN: ['2473-2575', '1556-6056', '1556-6064']
DOI: https://doi.org/10.1109/lca.2022.3215489