A novel reduced instruction set computer-communication processor design using field programmable gate array

نویسندگان

چکیده

In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit format and implemented using field programmable gate array (FPGA). The design of the RISC is facilitated like basic signals sine, cosine, square, modulation schemes amplitude modulation, shift keying, analog, digital quadrature modulation. Additionally, application-oriented traffic light, clock, linear feedback register are included in design. pipeline mechanism incorporated to enhance performance characteristics processor, hence allowing execution instructions more effectively. Also, Xilinx Virtex 7 family FPGA. device utilization analysis proposed FPGA along different families evaluated compared.

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ژورنال

عنوان ژورنال: International Journal of Reconfigurable & Embedded Systems (IJRES)

سال: 2023

ISSN: ['2089-4864', '2722-2608']

DOI: https://doi.org/10.11591/ijres.v12.i2.pp165-173