A phase-locked loop using ESO-based loop filter for grid-connected converter: performance analysis

High Speed Delay-Locked Loop for Multiple Clock Phase Generation

In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...

Software Phase Locked Loop Design Using C2000TM Microcontrollers for Single Phase Grid Connected Inverter

Grid connected applications require an accurate estimate of the grid angle to feed power synchronously to the grid. This is achieved using a software phase locked loop (PLL). This application report discusses different challenges in the design of software phase locked loops and presents a methodology to design phase locked loops using C2000 controllers for single phase grid connection applicati...

Grid-voltage Synchronization Algorithms Based on Phase-locked Loop and Frequency-locked Loop for Power Converters

Computer investigation of a sine and cosine based phase-locked loop for single phase grid connected inverter

This paper presents a new approach for PLL for synchronization with the public grid phase and frequency of grid-connected single phase inverter. The approach uses trigonometric transformations of the inverter output voltage and the grid voltage. The proposed mathematical model is then studied by means of computer simulation for different voltage amplitudes of the grid voltage as well as the inv...

Dual Phase Detector Based Delay Locked Loop for High Speed Applications

In this paper a new architecture for delay locked loops will be presented.  One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...