A Power-Efficient Multiplexer using Reversible Logic

A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

Reversible logic is becoming one of the best emerging design approaches for future computation of reversible logic having its more application in low power application. This logic is applied in the quantum computers, optical computing, communication and nanotechnology. In reversible logic approach generates the garbage input/output. In this paper design of proposed reversible logic multiplexer ...

Power Efficient Arithmetic Logic Unit Design using Reversible Logic

1. Laszlo B. Kish, Texas A&M University, Department of Electrical Engineering, College Station, TX 77843-3128, USA Received 16 July 2002; received in revised form 19 September 2002; accepted 19 September 2002, Communicated by C.R. Doering, “End of Moore’s law: thermal (noise) death of integration in micro and nano electronics.” 2. Trevor Pering, Tom Burd, and Robert Brodersen University of Cali...

E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion

Due to the outsourcing of chip manufacturing, countermeasures against Integrated Circuit (IC) piracy, reverse engineering, IC overbuilding and hardware Trojans (HTs) become a hot research topic. To protect an IC from these attacks, logic encryption techniques have been considered as a low-cost defense mechanism. In this paper, our proposal is to insert the multiplexer (MUX) with two cases: (i) ...

DESIGN AND ANALYSIS OF 4:1 MULTIPLEXER USING AN EFFICIENT REVERSIBLE LOGIC IN 180nm

Multiplexer’s square measure is a typical building block for data-paths, and is used extensively in a variety of applications together with the processors. In this paper authors have proposed a 4:1 multiplexer using PFAL and ECRL adiabatic logic design technique and compared with the Conventional CMOS Multiplexer. The basic approaches that we used for reducing energy/power dissipation in conven...

Novel Design of A 4:1 Multiplexer Circuit Using Reversible Logic