Adaptive Time-Triggered Multi-Core Architecture

The Time-Triggered Architecture

The Time-Triggered Architecture (TTA) provides a computing infrastructure for the design and implementation of dependable distributed embedded systems. A large real-time application is decomposed into nearly autonomous clusters and nodes and a fault-tolerant global time base of known precision is generated at every node. In the TTA this global time is used to precisely specify the interfaces am...

T-CREST: Time-predictable multi-core architecture for embedded systems

Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resultin...

A Hybrid Multi-core Architecture for Real-time Video Tracking

In this paper, we present an implementation of real-time video tracking on a novel reconfigurable multi-core architecture capable of reacting to changing workload while minimizing the number of active cores. The system is comprised of multiple processor cores executing sequential software threads, and hardware cores implemented in an FPGA executing dynamically reconfigurable hardware threads. S...

Tiled Multi-Core Stream Architecture

Conventional stream architectures focus on exploiting ILP and DLP in the applications, although stream model also exposes abundant TLP at kernel granularity. On the other side, with the development of model VLSI technology, increasing application demands and scalability challenges conventional stream architectures. In this paper we present a novel Tiled Multi-Core Stream Architecture called TiS...

Mode Handling in the Time-Triggered Architecture