An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement

In this work, we present a compact “adaptive downsampling” method that mitigates the nonlinearity problems associated with FPGA-based TDCs utilize delay lines. Additionally, generic allows for trade-offs between resolution, linearity, and resource utilization. Since is one of predominant issues regarding lines in TDCs, combined fact are utilized wide range TDC architectures (not limited to delay-line TDC), other implementations (e.g., Vernier or wave union TDCs), also different FPGA devices, can directly benefit from proposed adaptive method, no need either custom routing complex tuning converter. Furthermore, implementation-related challenges clock skew, measurement uncertainty, placement discussed propose an experimental setup utilizes only resources order characterize Although work was implemented Xilinx Virtex-6 device characterized under operational modes, successfully optimized converter’s utilization while retaining single-shot precision. The best performing (in terms linearity) implementation reached DNLrms INLrms values 0.30 LSB 0.45 LSB, respectively, precision (σ) 9.0 ps.