Area Efficient Layout Design of CMOS Comparator using PTL Logic
نویسندگان
چکیده
منابع مشابه
Analysis of Low Power and Area efficient CMOS Comparator Design
In this Paper presents a new dynamic comparator is compared in terms of their voltage, speed and power. A new dynamic comparator which shows lower input offset voltage and high load drivability than the conventional dynamic comparators. This comparator not only achieves low offset but also exhibit high speed and low power in its operation, which can be used for low power high speed ADC applicat...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2015
ISSN: 0975-8887
DOI: 10.5120/21784-5065