Bilayer tunneling field effect transistor with oxide-semiconductor and group-IV semiconductor hetero junction: Simulation analysis of electrical characteristics

Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

The IGFET or MOSFET is a voltage controlled field effect transistor that differs from a JFET in that it has a “Metal Oxide” Gate electrode which is electrically insulated from the main semiconductor n-channel or p-channel by a very thin layer of insulating material usually silicon dioxide, commonly known as glass. This ultra thin insulated metal gate electrode can be thought of as one plate of ...

Fast 1 kV metal-oxide-semiconductor field-effect transistor switch

Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics

We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a stro...

Simulation of Self-Heating and Temperature Effect in GaN-based Metal-Semiconductor Field-Effect Transistor

Two-dimensional electro-thermal simulations of GaN-based metal-semiconductor fieldeffect transistor are performed in the framework of the drift-diffusion model. The dependence of the hot spot temperature in transistors with many gates on the gate-to-gate pitch is studied. The case of SiC substrate is compared to the case of sapphire substrate. The ambient temperature effect on transistor perfor...

Engineering the Electron-Hole Bilayer Tunneling Field- Effect Transistor

The electron-hole (EH) Bilayer Tunneling FieldEffect Transistor promises to eliminate heavy-doping band-tails enabling a smaller subthreshold swing voltage. Nevertheless, the electrostatics of a thin structure must be optimized for gate efficiency. We analyze the tradeoff between gate efficiency versus on-state conductance to find the optimal device design. Once the EH Bilayer is optimized for ...