Chaining Optimization Methodology: A New SHA-3 Implementation on Low-End Microcontrollers

Since the Keccak algorithm was selected by US National Institute of Standards and Technology (NIST) as standard SHA-3 hash for replacing currently used SHA-2 in 2015, various optimization methods have been studied parallel hardware environments. However, a software environment, is much slower than existing family; therefore, use low limited environment using embedded devices such Wireless Sensor Networks (WSN) enviornment. In this article, we propose method that can be generally to break through speed limit SHA-3. We combine θ, π, ρ processes into one, reducing memory access internal state more efficiently conventional methods. addition, present new implementation proposed most constrained 8-bit AVR microcontroller. This method, which call chaining methodology, implicitly performs π process f-function while minimizing Through this, it achieves up 26.1% performance improvement compared previous an microcontroller reduces gap with family maximum. Finally, apply our Hash_Deterministic Random Bit Generator (Hash_DRBG), one upper algorithms function, prove applicability methodology on MCUs.