Chemical bond manipulation for nanostructure integration on wafer scale

Three Dimensional Integration and On-wafer Packaging for Heterogeneous Wafer-scale Circuit Architectures

Advanced Network Centric Warfare (NCW) systems are critical to the successful implementation of the Army’s Future Force. These systems require a new generation of circuits with deployable, agile, versatile, lethal, survivable and sustainable capabilities. Both manned and unmanned vehicles are required to established dominance in the battlefield via use of multi-band, agile, multifunctional mobi...

Wafer Scale Integration of Parallel Processors

A RAM-based Neural Network Architecture for Wafer Scale Integration

While the use of WSI technology to increase the integration density of RAM devices may not be cost effective (cf. Anamartic’s failed WSI RAMs [23]), low defect tolerance overheads, high testability, and low power consumption make memories ideal building blocks for WSI processor architectures. Indeed, this is reflected in the number of memory-based WSI devices manufactured to date [15,19,22,23,24].

On the Complexity of Wafer-to-Wafer Integration

In this paper we consider the Wafer-to-Wafer Integration problem. A wafer is a p-dimensional binary vector. The input of this problem is described by m disjoints sets (called "lots"), where each set contains n wafers. The output of the problem is a set of n disjoint stacks, where a stack is a set ofm wafers (one wafer from each lot). To each stack we associate a p-dimensional binary vector corr...

Wafer Scale Variation of Planarization Length in Chemical Mechanical Polishing

Chemical mechanical polishing (CMP) is widely used for pla-narization of advanced interconnect and shallow trench isolation structures in integrated circuit manufacture. Of particular concern is within-die variation in the interlevel dielectric or oxide thickness remaining after polish, due to pattern density variations across the die. 1 Recent modeling of CMP has shown that a " planarization l...