CMOS-compatible wafer-scale Si subulate array for superb switching uniformity of RRAM with localized nanofilaments

Resistive switching random access memory (RRAM) is one of the most promising candidates with high-density three-dimensional integration characteristics for next-generation nonvolatile technology. However, poor uniformity issue caused by stochastic property conductive filament (CF) impedes large-scale manufacture RRAM chips. Subulate array has been introduced into to minimize CF randomness, but methods are cumbersome, expensive, or resolution-limited preparation. In this work, Si subulate (SSA) substrates different curvature radii prepared a wafer-scale and nanoscale-controllable method fabrication. The SSA structure, which induces quasi-single few CFs formed in tip region (TR) device as evidenced high-resolution transmission electron microscopy energy dispersive spectroscopy characterization, dramatically improves cycle-to-cycle device-to-device uniformity. Decreasing radius TR significantly performance, including voltages, high/low resistance states, retention characteristics. improved can be attributed enhanced local electric field TR. proposed provides low-cost, uniform, CMOS-compatible, optimization strategy highly uniform devices.