Defect-Tolerant Architectures for Nanoelectronic Crossbar Memories

Crossbar-based Nanoelectronic Architectures

The last 40 years have seen an exponential increase in the number of transistors per processor. Along with this increase has been an exponential increase in processor performance. However, now that CMOS scaling has reached the deep submicron range, fundamental physical properties are limiting the further scaling of this technology. Nanoelectronic devices have recently been developed as one poss...

Defect-tolerant Logic with Nanoscale Crossbar Circuits

Crossbar architectures are one approach to molecular electronic circuits for memory and logic applications. However, currently feasible manufacturing technologies introduce numerous defects so insisting on defectfree crossbars would give unacceptably low yields. Instead, increasing the area of the crossbar provides enough redundancy to implement circuits in spite of the defects. We identify rel...

Fault-tolerant Architectures for Nanoelectronic and Quantum Devices

Defect-tolerant n2-transistor structure for reliable nanoelectronic designs

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by N-transi...

FRACTURE IST–2000-26014 Nanoelectronic Devices and Fault-Tolerant Architectures

Project funded by the European Community under the " Information Society Technologies " Programme (1998-2002)