Design and implementation of a single-chip 1-D median filter
نویسندگان
چکیده
منابع مشابه
Design and implementation of a single-chip 1-d median filter
The design and implementation of a 1-Dimensional median filter in VLSI is presented. The device is designed to operate on 8-bit sample sequences with a window size of 5 samples. Extensive pipelining and employment of systolic concepts at the bit level enable the chip to filler at rates up to 10 Mega-samples per second The chip is designed to be implemented with a X = 2.5ji NMOS technology and i...
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ژورنال
عنوان ژورنال: IEEE Transactions on Acoustics, Speech, and Signal Processing
سال: 1983
ISSN: 0096-3518
DOI: 10.1109/tassp.1983.1164203