Design of energy-efficient multiplier based on 3:2 compressor

<span>A multiplier circuit is one of the most important functional blocks many nano-electronic, control and automation applications. In this work, an energy-efficient reported based on a 3:2 compressor. The has been designed in three different parts. first part, partial product (PP) generator used. second products are reduced which termed as PPP (partial processing). Whereas third step final addition performed. PPs produced by using AND gates. two-phase. phase, Wallace tree logarithm used to reduce PPs. Whereas, phase half adder At last, step, carry-save computed. performance analysis evaluated compared with other circuits. shows improvements 20.55%-46% for power supply variation from 1.2 V 0.6 V. All simulations analyses have carried out Synopsys EDA tool.</span>