Design of low power pipelined ADC
نویسندگان
چکیده
منابع مشابه
Design of low power pipelined ADC
A design of 8 bits, 2.5V pipeline ADC is introduced in this paper. The comparator is the main improvement aiming at realizing low power dissipation. The latched comparator is adopted to achieve the specification. The design is implemented under 0.25um CMOS technology which achieves a power dissipation of 205.9mW.
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ژورنال
عنوان ژورنال: IJIREEICE
سال: 2014
ISSN: 2321-2004
DOI: 10.17148/ijireeice.2014.21219