Design of Parallel Decimal Floating-Point Arithmetic Unit for High-speed Operations

Design Exploration for Decimal Floating-Point Arithmetic

Commercial applications and databases typically store numerical data in decimal format. Currently, however, microprocessors do not provide instructions or hardware support for decimal floating-point arithmetic [ 1 ]. Consequently, decimal numbers are often read into computers, converted to binary numbers, and then processed using binary floating-point arithmetic. Results are then converted back...

A Floating-Point Unit for Arithmetic Operations

In this paper we present a design for a floating point unit partially compliant with the IEEE 754 floating point standard. The unit fully implements comparisons and partially implements floating-point addition and multiplication. It is fully parametrized and may be used with floating point numbers whose composite fields have widths of any desired length.

Software implementation of the IEEE 754R decimal floating-point arithmetic

The SNAP Project: Design of Floating Point Arithmetic Unit

In recent years computer applications have increased in their computational complexity. The industry-wide usage of performance benchmarks, such as SPECmarks, and the popularity of 3D graphics applications forces processor designers to pay particular attention to implementation of the floating point unit, or FPU. This paper presents results of the Stanford subnanosecond arithmetic processor (SNA...

Chapter 3 Decimal Floating Point Multipliers and MAC Unit