Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes

Abstract Vertically stacked horizontal nanosheet gate-all-around transistors seem to be one of the viable solutions toward scaling down below sub-7nm technology nodes. In this work, we compare electrical performance, including variability studies several transistor structure optimization. We explore impacts width and thickness on performance outline important design guidelines necessary for vertically FETs. An increase in complexity structures can lead significant device variability. Using numerical simulation, study characteristics fluctuations induced by random discrete dopants (RDD) metal grain granularity (MGG) (GAA) transistors. use 3-D quantum-mechanically corrected transport models simulation. It is observed that σV TH due MGG 12% higher than RDD while strongly influences I ON. The statistical simulation results predict presence combined threshold voltage variation (σV ) nanoscale devices. This approach may applied different types variability, geometry device, vertical lateral dimensions transistor, biasing conditions.