Error Estimation and Error Reduction With Input-Vector Profiling for Timing Speculation in Digital Circuits
نویسندگان
چکیده
منابع مشابه
Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates
Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and ...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 2019
ISSN: 0278-0070,1937-4151
DOI: 10.1109/tcad.2018.2808240