FPGA accelerator for floating-point matrix multiplication
نویسندگان
چکیده
منابع مشابه
FPGA accelerator for floating-point matrix multiplication
This study treats architecture and implementation of a FPGA accelerator for double-precision floating-point matrix multiplication. The architecture is oriented towards minimising resource utilisation and maximising clock frequency. It employs the block matrix multiplication algorithm which returns the result blocks to the host processor as soon as they are computed. This avoids output buffering...
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ژورنال
عنوان ژورنال: IET Computers & Digital Techniques
سال: 2012
ISSN: 1751-8601
DOI: 10.1049/iet-cdt.2011.0132