FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings

Numerous experiments require low latencies in the detection and processing of neural brain activity to be feasible, order a few milliseconds from action reaction. In this paper, design for sub-millisecond communication spiking detected by an array 32 intracortical microelectrodes is presented, exploiting real-time provided Field Programmable Gate Array (FPGA). The embedded commercially available RHS stimulation/recording controller Intan Technologies, that allows recording signals performing IntraCortical MicroStimulation (ICMS). Spike Detector (SD) based on Smoothed Nonlinear Energy Operator (SNEO) includes novel approach estimate RMS-based firing-rate-independent threshold, can tuned fine detect both single Action Potential (AP) Multi Unit Activity (MUA). A low-latency SD together with ICMS capability, creates powerful tool Brain-Computer-Interface (BCI) closed-loop relying neuronal activity-dependent stimulation. also includes: third Butterworth high-pass IIR filter Savitzky-Golay polynomial fitting; privileged fast USB connection stream spikes host computer sub-milliseconds latency Universal Asynchronous Receiver-Transmitter (UART) protocol send detections receive triggers. source code instruction project found GitHub.