Gate and Substrate Currents in Deep Submicron MOSFETs

Gate and Substrate Currents in Deep Submicron MOSFETs

Gate capacitance of deep submicron MOSFETs with high-K gate dielectrics

We study gate capacitance of deep submicron MOSFETs with high-K gate dielectrics. Schrödinger’s equation is solved by applying an open boundary condition at silicon-gate dielectric interface. Self-consistent numerical results reveal that accounting for wave function penetration into the gate dielectric causes the carrier distribution to be shifted closer to the gate dielectric. This effect incr...

Scaling of InGaAs MOSFETs into deep-submicron

We have demonstrated high-performance deep-submicron inversion-mode InGaAs MOSFETs with gate lengths down to 150 nm with record Gm exceeding 1.1 mS/μm. Oxide thickness scaling is performed to improve the on-state/off-state performance and Gm is further improved to 1.3 mS/μm. HBr pre-cleaning, retro-grade structure and halo-implantation processes are first time introduced into III-V MOSFETs to s...

A Simple General-purpose I-V Model for All Operating Modes of Deep Submicron MOSFETs

A simple general-purpose I-V model for all operating modes of deep-submicron MOSFETs is presented. Considering the most dominant short channel effects with simple equations including few extra parameters, a reasonable trade-off between simplicity and accuracy is established. To further improve the accuracy, model parameters are optimized over various channel widths and full range of operating v...

Gate Engineering for Deep-Submicron CMOS Transistors

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET’s. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET’s is investigated. The suppression of...