Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System

Decision trees are machine learning models commonly used in various application scenarios. In the era of big data, traditional decision tree induction algorithms not suitable for large-scale datasets due to their stringent data storage requirement. Online have been devised tackle this problem by concurrently training with incoming samples and providing inference results. However, even most up-to-date online still suffer from either high memory usage or computational intensity dependency long latency, making them challenging implement hardware. To overcome these difficulties, we introduce a new quantile-based algorithm improve Hoeffding tree, one state-of-the-art models. The proposed is lightweight terms both demand, while maintaining generalization ability. A series optimization techniques dedicated investigated hardware perspective, including coarse-grained fine-grained parallelism, dynamic memory-based resource sharing, pipelining forwarding. Following this, present Hard-ODT, high-performance, hardware-efficient scalable system on field-programmable gate array (FPGA) system-level techniques. Performance utilization modeled complete early fast analysis tradeoff between design metrics. Finally, propose flow which applied FPGA run-time power monitoring as case study. Experimental results show that our outperforms method, leading 0.05% 12.3% improvement accuracy. Real implementation demonstrates $384\times $ notation="LaTeX">$1581\times speedup execution time over design. modeling strategy Hard-ODT achieves an average prediction error within 4.93% commercial gate-level estimation tool.