Improved Hopfield Network Optimization Using Manufacturable Three-Terminal Electronic Synapses

We illustrate novel optimization techniques via simulations for Hopfield networks constructed from manufacturable three-terminal Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) synaptic circuit elements. first present a computationally-light, memristor-based, highly accurate static compact model the SONOS synapses used in our simulations. then show how to exploit analog errors programming resistances and current leakage, continuous tunability of enable transient chaotic group dynamics, accelerate convergence network. project improvements energy consumption time solution relative existing CPUs GPUs by at least 4 orders magnitude, also exceed projected performance two-terminal memristor-based crossbars addition 100-fold increase error-resilient array size (i.e. problem size).