Layout-synthesis techniques for yield enhancement
نویسندگان
چکیده
منابع مشابه
Layout - S ynthesis Techniques for Yield Enhancement
Several yield enhancement techniques are proposed for the last two stages of VLSI design, i.e., topological/symbolic and physical layout synthesis. Our approach is based on modiications of the symbolic/physical layout to reduce the sensitivity of the design to random point defects without increasing the area, rather than fault tolerance techniques. A layout compaction algorithm is presented and...
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ژورنال
عنوان ژورنال: IEEE Transactions on Semiconductor Manufacturing
سال: 1995
ISSN: 0894-6507
DOI: 10.1109/66.382281